FPGA-based System on Chip Design - Lecture
The aim of this course is to provide students with a solid understanding of designing complex FPGA Sys-tem on Chip (SoC) architectures, starting with the creation of high-level functional specifications up to the design, implementation and testing on FPGA SoC platforms using hardware description and software programming languages. In particular, the course will cover
- an introduction to FPGA based System on Chip design – Applications, limitations and challenges.
- the anatomy of modern embedded System on Chip architectures: The hard processor system and FPGA fabric, booting and configuration, PCB issues and design strategies.
- RTL hardware design including simulation, and verification using SystemVerilog HDL.
- methodologies for successful timing closure, multi-clock domains and synchronization tech-niques.
- design strategies for architecting for performance, area and power.
- embedded processors in SoC FPGAs: Hard and soft-processor systems, on-chip bus systems
the design and implementation of custom hardware accelerators: Integration of co-processors, ISA customization in soft-processor systems, design of customized HW/SW interfaces.
- the optimizing of design metrics using HW/SW co-design approaches.
- High-Level-Synthesis: Algorithm and interface synthesis, design evaluation and optimization.
FPGA-based System on Chip Design – Lab
The lab focuses on teaching practical skills related to FPGA based SoC design using C and SystemVerilog:
- Design and implementation of custom hardware accelerators (Co-Processors, ISA extensions).
- HW/SW integration of custom accelerators into existing FPGA based SoC architectures followed by profiling and benchmarking of the respective solutions.
