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Digital Finite State Machine Design

Description
This Module will enable the student to analyse and design digital circuits using state machine and other techniques and to assess and evaluate real world effects like setup and hold time issues, signal reflections and relevant real-world issues.

ECTS credits
5

Teaching Language
English

Exam Language
English

Support Materials Language
English

Basic Learning Outcomes

Managing Entity (faculty)
School of Electrical and Electronic Engineering (TU Dublin)