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Digital System Design - UTCN
CS11.00

Description
 | VHDL hardware description language – basic design units, signals
 | VHDL hardware description language – generics, constants, operators, data types, attributes
 | VHDL hardware description language – sequential domain
 | VHDL hardware description language – concurrent domain
 | Creating testbenches for simulating and testing circuits in VHDL
 | Automata (Finite State Machines) Theory – classification, definitions, formal models
 | Microprogramming
 | Microprogrammed Devices
 | Designing Synchronous Automata
 | Analysis and Design (Synthesis) of Asynchronous Automata (I)
 | Analysis and Design (Synthesis) of Asynchronous Automata (II)
 | Automata Identification
 | Lossless Machines
 | Linear Automata

ECTS credits
5

Teaching Language
English

Exam Language
English

Support Materials Language
English

Basic Learning Outcomes

Managing Entity (faculty)
Automation and Computer Science Faculty - UTCN